Friday, September 21, 2007
FPGA Project Completed!
This semester I has enrolled in course Hardware Synthesis Lab. It was about designing an ASIC (Application Specific Integrated Circuit) using HDL (Hardware Description Language). With HDL, the circuit designers do not have to interfere with primitive elements such as AND, OR gates. Instead, they write a module specification in a human-readable language (VHDL, Verilog) and let the synthesizer do the rests. In my class, everyone has to use Verilog with Xilinx ISE Webpack with Xilinx Spartan-3 Starter kit board.
The final project assignment is to design the classic Pong game. The video is displayed through VGA interface in 640 x 480 8 colors mode. And the users can also control their paddles using PS/2 keyboard.
It took me a week to finish this project, Here is its screen shot. (I had took this photo with my phone. The famous PrntScrn is useless in this situation :P )
The really hard part in this project is to make the user interface looks good while you can use only 8 colors! My lab partner, Oei, helped me a big part in choosing the color for this design. To make the screen more beautiful, I decided to put my effort into finding a way to load an image data onto my board. It took me hours reading through Xilinx documentations to find a method to load initial values for Blocked RAM on Spartan-3. I will write an entry on this later when I am free.
In conclusion, this course show me what I can get from little Spartan-3 FPGA board. And how hard it is to make a little Pong game.
I would rather code this in Java or C# and get the result in a blink if I ever need to make my own version of Pong next time o__O