Note: I will assume that the readers know how to design ASIC using Verilog language with Xilinx Webpack and have some background in computer programming.
First, since I was going to use 640x480 8-color mode, so I prepared 8-color bitmap images of in-game components. These are few examples.
To display these images, we need to store their pixel data somewhere in our circuit. There are few options.
- Hard-code the static wire or reg variables, which store pixel data, in the Verilog code. This is going to be easy. But you will suffer from long synthesis, post-place and route time. The size of .v files are going to be unacceptable big too.
- Utilize the Block RAMs available as external component on Xilinx Spartan-3 FPGA board. Just set the initial values of these Block RAMs to the pixel data of our images.
No matter which way you chose, we need to convert .jpg, .gif , .png, .bmp, etc. images data into easy-to-understand pixel data. This can be done via a little programming. The following Java program prompts user for an image and convert it to Coefficients File (.coe) for use as initial value of Block RAMs. The format of Coefficient File can be found in the Xilinx documentation I mentioned recently.
The program generates two files, name.coe for color images and name.bw.coe for black and white images. BW images consume less space.
You can now add new ROM module to your design using Xilinx Core Generator from with Xilinx Project Navigator. The detailed instructions on how to do this can also be found on the document I mentioned before. But I am kind enough to provide you this less-detailed screen shots :)
Create new source and select IP (Coregen & Architecture Wizard)
For this kind of use, a read-only Single Port Block Memeory would be enough.
You can specify some memory attributes here.
This is the most important part. You have to tick the "Load Init File" checkbox and click "Load File ..." button then choose the generated .coe file or .bw.coe file.
You can click on the "Show Coefficients" button to make sure that your file properly loaded.
Finally, click on the "Generate" button to generate your ROM module. Your ROM is now ready to use :)
I hope this helps.